VHDL programming Example OR gate, half adder, and full adder using half adder

Published: 01 November 2020
on channel: MNS Tutorial

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In this tutorial, we describe how to design a simple OR gate, bit compare, half adder, and full adder components using VHDL. You will learn how to combine several component or files in one design. For example we create a full adder using two copy of half adders.

Shortcuts:
0:00 Introduction
1:29 OR gate simple example
16:34 Bit compare
20:41 Half adder
25:15 Full Adder using half adder

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