Full adder using half Adder | Gate 2023

sta lec37 interview question part2 | static timing analysis tutorial | VLSI

sta lec36 - Interview Questions Part1 | static timing analysis tutorial | VLSI

PD Lec 67 - Global and Detail Routing | VLSI | Physical Design

PD Lec 66 - Routing Concepts | VLSI | Physical Design

PD Lec 65 - Introduction to Routing | VLSI | Physical Design

PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design

perl lecture12: data extraction using regular expression | regex | pattern matching

PD Lec 63 - Post CTS Optimization | VLSI | Physical Design

PD Lec 62 - CTS Analysis | VLSI | Physical Design

PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design

PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design

Full adder using half Adder | Gate 2023

PD Lec 59 - Master, Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design

PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design

PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design

Half Adder | GATE Exam | Digital Electronics | Logic Gates | Easy Explanation

PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design

PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design

8x1 Multiplexer using 2x1 MUX | GATE Exam | Digital Electronics | MUX Tree Basic | Easy Explanation

PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design

4x1 Multiplexer using 2x1 MUX | GATE Exam | Digital Electronics | MUX Tree Basic | Easy Explanation

PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design

PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design