Binary Counter with Parallel Load
Counters employed in digital systems quite often require a parallel‐load capability for transferring an initial binary number into the counter prior to the count operation. Figure shows the top‐level block diagram symbol and the logic diagram of a four‐bit register that has a parallel load capability and can operate as a counter. When equal to 1, the input load control disables the count operation and causes a transfer of data from the four data inputs into the four flip‐flops. If both control inputs are 0, clock pulses do not change the state of the register.
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