Coding and Debugging RISC-V
As monolithic device scaling continues to wind down and evolve toward increasingly heterogeneous designs, it has created an inflection point for chip architects to create customized cores that are much more energy efficient and faster than off-the-shelf processors. Zdeněk Přikryl, CTO of Codasip, talks with Semiconductor Engineering about where RISC-V fits into this picture, using a modular ISA and custom instruction layer to enable differentiation. He also examines the various steps to develop code for RISC-V designs using a front-end high-level programming language, followed by optimization, to produce an assembly or object file, and looks at at what LLVM brings to the table.
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