16-BIT CPU with RegisterFile (Fibonacci Sequence) Logisim Evolution. Python.
In this video, I show off my newest CPU project.
It is a 16-BIT CPU with 64k ram, 16 Registers (9 of them are general purpose Registers), a Stack with 256 addresses, a TTY display, and an 8 x 16 matrix display.
It has 2 separate BUS's, one for DATA and one for Addresses.(I only did this to speed the computer up.)
The control unit and instruction set architectures are almost the same as my 4-BIT CPU. This instruction set is more robust than the 4-BIT version. The Conrtol Unit is made out of 17 Decoders and 102 Buffers.
The program in this video calculates the fibonacci sequence and then splits each number into 5 digits, then converts the 5 digits to ascii and then prints them on the TTY display.
Next, I am going to write a program that lets you save and load a text file and do simple math problems. At some point, I plan on coding pong for it as well.
The Current file for this computer are available on my Discord.
If you would like to help me improve the quality of my videos, here is a link to my Patreon.
/ ajax123z
If you would like to join the free channel of my Discord, here is the link.
/ discord
Here is a link to Logisim-Evolution.
https://github.com/logisim-evolution/...
If you have any Questions or Suggestions, comment them below.
If you enjoy my content, please Like and Subscribe.
Thanks for Watching!
On this page of the site you can watch the video online 16-BIT CPU with RegisterFile (Fibonacci Sequence) Logisim Evolution. Python. with a duration of hours minute second in good quality, which was uploaded by the user Ajax 01 January 2025, share the link with friends and acquaintances, this video has already been watched 311 times on youtube and it was liked by 21 viewers. Enjoy your viewing!
