Example 07. Logic expression minimization using K-maps. 5 variables function.

Example 11. BCD encoding checker.

Example 09. Maximum temperature detector.

Example 10. Maximum/minimum temperature detector.

Example 07. Simple encoders design using K-maps.

Example 08. Parity generator design

Example 08. Parity generator design using Verilog.

Example 06. Logic function design using 8:1 multiplexers.

Example 06. Logic function design using 4:1 multiplexers.

Example 05. Simple logic function design using multiplexers.

Example 04. Multiplexer design.

Example 01. Decoder design

Example 02. Logic function design with decoders and logic gates.

Example 15. Logic circuit timing analysis with hazards

Example 13. Logic circuit functional analysis

Example 14. Logic circuit timing analysis

Example 12. Logic circuit design with "don't cares"

Example 10. Combinational circuit design

Example 11. Combinational circuit design with NAND gates only

Example 09. Combinational circuit design

Example 08. K-map minimization from different representations

Example 07. Logic expression minimization using K-maps. 5 variables function.

Example 07. Logic expression minimization using K-maps (Product of Sums form)

Example 07. Logic expression minimization using K-maps (Sum of Products form)

Example 06. Logic expression minimization using logic expressions