CPU cache | cache memory organization | static vs dynamic RAM | Bad code and CPU cache | Performance
CPU cache plays a huge role in improving the overall performance of a computer. The influence of spatial locality and temporal locality in a program is exploited by the CPU cache and used for improving the performance multifold.
Computer organization and architecture is an interesting and important topics. But in recent times it overlooked by programmers. Only compiler writers and OS designers give importance to it. Rest all taking it for granted. But having a good understanding of the underlying computer organization and architecture design will help in making an informed decision while designing the application load.
Recent computers are following modified von Neuman architecture or Harvard architecture. Both include transparent caches. Though they are transparent, they play a significant role in overall system performance.
The instruction cycle in a computer organization is a critical factor in performance. There are multiple pipelines to maximize the utilization of all the components of a CPU. In a CISC CPU like Intel, there are up to 20 levels in a pipeline. The instruction cycle in a computer organization is heavily dependent on the CPU cache.
There are three sections in this video. First, we'll see what is a CPU cache and how it is implemented. Second, we'll see how it is improving the overall computer performance. At last, we'll see how a bad can produce an adverse effect in overall performance. As a programmer, you not only give importance to the algorithm but also the underlying computer system architecture and manage your dataset accordingly (or vice versa).
We always think that RAM is the main memory. But both CPU cache and Main memory are implemented with RAM. There are two types of RAM. Static RAM (SRAM) and Dynamic RAM (DRAM). A CPU cache is implemented with static RAM and the Main memory of a computer is implemented with Dynamic RAM.
Static RAM is approximately 100 times faster the dynamic RAM. Then why can't we use SRAM for the main memory? Because of its transistor logic, SRAM is so big and power-hungry. A typical laptop will not have sufficient space and battery capacity to power 8GB of SRAM. Maybe in a system that is completely designed for gaming, the gaming ram can be developed with SRAM. We'll see why the size and power necessity is different for SRAM and DRAM.
As cache size (SRAM) is limited, it can hold only a certain amount of data. As a programmer, you should make the most of it. If you write a code that gets a lot of cache-miss and hits the main memory, it is going to slow down your application 100 or 200 times. Though preloading is going to handle it, it can't completely avoid the adverse effect. Preloading means data or instruction gets loaded into the cache from the main memory even before it is required. We'll see a microbenchmark that exposes this bug. And what is the optimal dataset size to hit maximum performance from a computer system based on its architecture?
In the microbenchmark, time is calculated in CPU clock cycles. Time measurement is clock-time will be biased based on the CPU's speed. But it is calculated in the CPU clock cycle, so graphs of multiple cache memory organizations can be compared directly. Processor organization in computer architecture is depending on the cache memory organization and memory organization. To compare the performance benefit of each organization, there should be a metric that is not affected by the processor speed alone. In this case, it is the processor clock cycle.
CPU cache | cache memory organization | static vs dynamic RAM | Bad code and CPU cache | Performance
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